A Novel Pipelined Architecture for 4X4 Inversion Matrix of Kalman Filters Using Verilog in ASIC

Abstract

A novel pipelined systolic array-based architecture for 4X4 matrix inversion is proposed. It is suitable for ASIC implementations as it is used for in Kalman filters. The 4X4 matrix inversion is implemented in verilog language for enabling the user for different size of Kalman filters suitable for different applications. It is scalable for different matrix size and as such allows employing parameterization that makes it suitable for customization for application-specific needs. The proposed architecture consists of pipeline registers, an innovative logic control unit, and a segmented Look up Table division scheme. This new proposed architecture has an advantage of reduced processing element complexity. The ASIC implementation architecture is useful to enable the novel pipelined systolic array for the quickest operation of Kalman filter. The precision error resulted is in the allowable range and it does not affect the performance of the overall system.