REDUCING ELECTRICAL SYSTEM HARMONICS BY RELOCATION OF POWER FACTOR CORRECTION CAPACITORS

Abstract

The objective of the paper is to present the observations and findings of a methodology for reducing current and voltage harmonics by relocating the Power Factor Correction (PFC) capacitors already installed in a paper mill. The 415V medium voltage (MV)bus in the mill is supplied by a 11kV/433V, 1.6 MVA transformer and feeds induction motors, Variable Frequency Drives and lighting load. Power Factor was manually maintained almost at unity with plain capacitors at the panel. A previous study using Power Quality Analyser C.A 8332 revealed that the quantum of harmonics is more than the desirable limits. Subsequently, the present study was done using a low cost harmonic indicator and an Energy Management System. Harmonic data were recorded on a continuous basis for various product runs. This revealed that original harmonic current generated due to the VFDs in the network was only 14A. This was magnified to 136A for a specific product run when the load current was 1033A. In another product run it was magnified to 266A when the load current was 548A. Behavior of transformer, induction motors and plain capacitors in the network was studied at harmonic frequencies when these linear devices are in parallel with nonlinear loads. Magnification of harmonics took place due to the power factor correction (PFC) capacitors at the MV panel. By relocating 50% of the PFC capacitors nearer to the linear loads, the total harmonic current was reduced to 130A from the previous value of 266A. It