DESIGN AND ANALYSIS OF NEW LOGICAL LOW POWER FULL ADDER WITH LOW POWER TECHNIQUES

Abstract

In this work, a logical 1-bit full adder design employing complementary metal–oxide–semiconductor (CMOS) logic is described. The schematic plan was implemented using Microwind 9.1 version. In this full adder, numbers of transistors are reduced by logicism. Consequently average power and layout area also reduced. The proposed full adder is compared with hybrid full adder utilizing CMOS logic and transmission gate logic. The simulation results of proposed circuit for 1.2-V supply at cmos 0.12µm technology, the average power consumption is 9.079 μW and layout area 213.8µm2 both performance parameters are reduced when compared to hybrid full adder. Hybrid full adder has 14.005 μW power consumption and 299.4 µm2 layout area. Further reducing power the proposed full adder was implemented along with some low power techniques and their results are tabulated.