REDUCING TEST APPLICATION TIME THROUGH TEST SUB-PATTERN RE-USE

Abstract

Test application time is a major factor of the cost associated with the scan technique. On one extreme test application time can be drastically reduced by using built-in self-test (BIST). However, the quality of random test pattern used by BIST is low. On the other extreme, automated test equipment based testing using quality automatic test pattern generation is very time-consuming. Research in the area of economics of test application is directed towards finding a good blend of the two extremes to arrive at a workable optimal hybrid. A novel method for achieving this hybrid is presented in this paper. The approach used consists of a modification of the scan architecture and the development of a matching algorithm. The modified scan architecture involves the addition of a multiple-input signature register (MISR) to the scan chain. This way test responses are not captured in the scan chain but, rather, are compressed in the MISR. The proposed algorithm then takes advantage of repeated patterns in test vectors, by rearranging them such that those with matching patterns are adjacent to each other. An illustrating of how the algorithm works is also presented.